A plasma addressed display device in which a plasma cell and an electro-optical display cell are laminated via a dielectric sheet has been proposed in U.S. Pat. No. 4,898,149 to Buzak (issue date: Jan. 23, 1990), U.S. Pat. No. 5,077,553 to Buzak (issue date: Dec. 31, 1991), and U.S. patent application Ser. No. 07/837,961 for an Electro Optical Device, filed by Shigeki Miyazaki on Feb. 20, 1992. The disclosure of the three above noted references are hereby incorporated herein.
FIG. 6 shows a circuit equivalent to a part of a plasma addressed display device. In FIG. 6, reference numeral 101 denotes an equivalent circuit for one picture element. CL denotes capacitance of a liquid crystal layer 7 for one picture element, CS and RS denote capacitance and resistance of a dielectric sheet 3, respectively, SW denotes a virtual switch (sampling switch) composed of a discharge channel 12, and CP and RP denote capacitance and resistance of a plasma section formed by barrier ribs 10 or the like, arranged in parallel with the virtual switch SW. In writing, the virtual switch SW is turned on by plasma discharge, and the voltage difference between data voltage DS and anode voltage VA is divided by the capacitance CS and CL and applied to the liquid crystal layer 7, by which the writing of data voltage DS is performed.
FIGS. 7A-7D show the relationship between data voltage DS (DS(1)-DS(m)), anode voltage VA, cathode voltage VK (VK(1)-VK(n-1)), etc. As shown in FIG. 7, the data voltage DS is supplied to data electrodes 5 (5(1)-5(m)) by a liquid crystal driver 21 for the writing period tw for each line, and the data electrodes 5 is at zero level for other periods. The data voltage DS is outputted from the liquid crystal driver 21 by being inverted for each one line and for each one field with (VH+VL)/2 being the center. Here, VH denotes positive dc voltage, and VL denotes negative dc voltage.
As shown in FIG. 7B, the anode voltage VA, outputted by an anode invert circuit anode 24, is outputted by being inverted for each one line and for each one field with (VH+VL)/2 being the center. Thereupon, the data voltage DS and the anode voltage VA are inverted alternately for one line and for one field, so that the liquid crystal layer 7 is ac driven.
The anode voltage VA changes alternately into VH and VL for one line as shown in FIG. 7B. The voltage difference between data voltage DS and anode voltage VA, and in turn the voltage applied to a series circuit of the liquid layer 7, dielectric sheet 3, and virtual switch SW changes as shown in FIG. 7D, so that there is a predetermined voltage difference even for the periods other than the writing period tw. As seen from the equivalent circuit in FIG. 6, the dielectric sheet 3 and the plasma section have finite resistances RS and RP, respectively, and an unnecessary voltage is applied to the liquid crystal layer 7 even for the periods other than the writing period tw, resulting in application of dc component to the liquid crystal layer 7. This application is undesirable because it may cause the deterioration in display characteristics such as the image retention of liquid crystal.